This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-010242, filed Jan. 18, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a data reading technique of a semiconductor storage apparatus, particularly to a fast data reading technique.
2. Description of the Related Art
When a semiconductor storage apparatus (e.g., NOR type flash memory) is accessed at random, a series of reading operation including: selecting a cell for each address input; sensing cell data; and outputting the data is repeated. Therefore, a certain given time is required, and the data cannot be outputted faster.
On the other hand, a serial access operation includes: selecting cells corresponding to a plurality of addresses present on the same word line at the same time; sensing the data; latching the sensed data; and sequential outputting the latched data in synchronization with a clock from the outside. Therefore, a fast data reading is apparently realized.
Furthermore, when the latched data is sequential outputted, a next group of cells are sensed in a chip. Since a so-called xe2x80x9cpipeline readingxe2x80x9d is performed, an internal reading delay can be eliminated in and after a first access, and the fast data reading is enabled.
The xe2x80x9cpipeline readingxe2x80x9d has heretofore been realized by dividing a memory cell array into two, and disposing a decoder and sense amplifier in the two arrays, respectively. Therefore, a chip area has largely increased.
A semiconductor integrated circuit device according to an aspect of the present invention comprises: a memory cell array; a row decoder which selects a row of the memory cell array; a sense amplifier which senses a plurality of data corresponding to a plurality of addresses from the memory cell array; a column gate in which two or more stages are connected in series, and which selects a column of the memory cell array and electrically connects the selected column to the sense amplifier; a column gate driving circuit which selects and drives the column gate; a data latch which latches the plurality of data sensed by the sense amplifier; a multiplexer which sequentially selects the data corresponding to a predetermined address from the plurality of data latched by the data latch; and an address control circuit which reverses a driving signal to drive at least one stage of the column gate with the two or more stages connected in series and selects columns designated by a plurality of addresses selected next to the plurality of addresses, during sequential selection of the data corresponding to the predetermined address by the multiplexer.